Low-Latency Burst Error Detection and Correction in Decision-Feedback Equalization

This article describes low latency, zero overhead DFE burst error correction technique. Without any encoder or decoder the proposed technique makes use of existing pre-cursor ISI to detect and correct errors on a data. The implemented proof-of-concept 2-tap prototype in 65nm CMOS operates at 16 Gb/s compensates 32 dB loss consuming 58 mW only. With an additional 18 mW, receiver enables capability that translates 2-to-6 SNR gain depending magnitude. Experimental results demonstrate for lossy channels where is 60% higher main, this outperforms RS(528, 514) without with much lower latency power consumption.